#MODELSIM ALTERA WINDOWS#

i guess modelsim project file (.mpf) somehow remembered that sdo file MUST be located into modelsim project's main folder. i have added the address to sdo file but it didnt work. i have tried to give address to it, in modelsim there is an option SDF address. now when you create your modelsim project elsewhere and simulate it, the modelsim project file somehow finds the correct sdo.Д«ut in time, when you re-launch modelsim simulation it may loose sight of sdo file that was located into your quartus project. quartus compiles it, renames it to sdo and places into your quartus project->simulation->modelsim folder. it is important to take it from your project's folder each time you recompile it sdo file is actually sdf. Please can you help me and remember that I'm a beginner!ДЄllright,do not use default sdo files. What did I do wrong? I also added my testbench (top.v) in quartusii simulation settings, where i selected 'compile test bench'. (errno = ENOENT)# ** Error: (vsim-SDF-3445) Failed to parse SDF file 'DE1_Default_v.sdo'.# Time: 0 ps Iteration: 0 Region: /punchARM File: C:/FPGA/punchARM/testbench/top.v# Error loading design Vsim -L C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii work.punchARM# vsim -L C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii work.punchARM # Loading work.punchARM# Loading work.pancham# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_lcell_comb# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_lcell_ff# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_io# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_mux21# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_dffe# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_asynch_io# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_clkctrl# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_mux41# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.cycloneii_ena_reg# ** Error: (vsim-SDF-3894) DE1_Default_v.sdo: Compiled SDF file was not found.# Loading C:/altera/11.0sp1/modelsim_ase/altera/verilog/cycloneii.CYCLONEII_PRIM_DFFE# ** Error: (vsim-7) Failed to open SDF file 'DE1_Default_v.sdo' in read mode.# No such file or directory. # Compile of DE1_Default.vo was successful.# Compile of top.v was successful.# 2 compiles, 0 failed with no errors.

The Transcript window shows an error now:

#MODELSIM ALTERA WINDOWS#

when the windows pops up, I select my top.v design (I had to add the cycloneii library, otherwise it gives me a long list of errors) then i do. After compiling i click on simulate->start simulation. My project in ModelSim-Altera contains a. I compiled a project in ModelSim-Altera successfuly and my design i want to simulate is designed for a cycloneii FPGA.

I have a prblem with my ModelSim-Altera 6.6d (Quartus II 11.0sp1) Starter Edition: I'm a beginner to the world of Simualtion:)

2022.03

Modelsim altera